The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a transistor having a vertical channel in the semiconductor device and a method for fabricating the same.
Recently, a research on a transistor having a vertical channel is actively progressed to increase the degree of integration of semiconductor devices.
FIG. 1A illustrates a plane view of a typical transistor having a vertical channel and FIG. 1B illustrates a cross-sectional view of a cell taken along a line A-A′ in FIG. 1A. The plane view in FIG. 1A is taken along plane cut out the line A-A′ while maintaining a height of a dotted line in FIG. 1B.
Referring to FIGS. 1A and 1B, a plurality of semiconductor pillars P is formed over a substrate 11. A pillar P includes a substrate material and has a portion which is vertically protruding from the substrate 11. Furthermore, as shown in FIG. 1A, the pillars P are arranged in a first direction and a second direction crossing the first direction. The pillar P has an upper part, a middle part and a lower part. In other words, the pillar P has a drain region D, a channel region C, and a source region S. The channel region C connects the drain region D and the source region S.
An electrode 13 is formed surrounding outside of the middle part of the pillar P, the channel region C. An insulation layer 12 is formed between the surrounding electrode 13 and the pillar P. A damascene word line 14 is formed extending along the first direction while electrically connecting neighboring surrounding electrodes on sidewalls of the surrounding electrode 13. The reference numerals 15 and 16 represent a first inter-layer insulation layer and a second inter-layer insulation layer, respectively.
In a semiconductor device including the transistor that has the above mentioned vertical channel structures, a word line is formed with the surrounding electrodes 13 and the damascene word line 14. In such semiconductor device, a width of the damascene word line 14 is limited by the surrounding electrodes 13. Thus, resistance of the word line is determined by the surrounding electrodes 13.
Since the surrounding electrodes 13 and the damascene word line 14 are generally formed of polysilicon, the resistance of the word line is highly increased.